(a) Field of the Invention
The present invention relates to a semiconductor integrated circuit and, more particularly, to a semiconductor integrated circuit wherein a bipolar transistor and a MOSFET are formed on a common semiconductor substrate.
(b) Description of the Related Art
A semiconductor integrated circuit in which a MOSFET and a bipolar transistor are formed on a common semiconductor substrate is known as a BiCMOS integrated circuit (referred to as "a BiCMOS IC" hereinafter). A conventional method for manufacturing a BiCMOS IC having an LDD (Lightly Doped Drain) structure will be described first.
FIG. 1 is a cross-sectional view showing a BiCMOS IC in a process step of a first conventional method for manufacturing the same. A polysilicon layer 53 and a tungsten silicide layer 54 are formed in this order on a gate oxide film 52 formed on a semiconductor substrate 51. The polysilicon layer 53 and the tungsten silicide layer 54 are then patterned to form a gate electrode.
For obtaining an LDD structure, an oxide film is subsequently grown covering the entire surface of the substrate, which is followed by an anisotropic etching to form sidewall spacers 55 on both sides of the gate electrode. Since the tungsten silicide layer 54 is used as an etch-stop layer during the anisotropic etching, the tungsten silicide layer 54 is back-sputtered by plasma ions so that tungsten particulates scatter into an ambient atmosphere.
The scattered tungsten particulates adhere onto the surface of a base region in a bipolar transistor exposed to the reaction atmosphere. If the BiCMOS IC is manufactured leaving the tungsten particulates as they are, the tungsten particulates will induce a leakage current from the base region. Hence, it is necessary to remove the tungsten particulates out of the base region.
Accordingly, after the etching for forming the sidewall spacers is finished, a slight sputter etching with argon ions is performed on the base region, with the surface of the substrate except for the base region being covered by a photoresist pattern. Then, after forming a thin oxide film, the base region is doped with an impurity, following which an emitter electrode is formed, whereby a bipolar transistor is obtained. Thus, a BiCMOS IC having a MOSFET of the LDD structure and a bipolar transistor is manufactured.
The first method requires the step for covering the silicon substrate except for the base region with a photoresist pattern and the step for sputter-etching the silicon substrate in the base region. Especially, the method involves the time-consuming step for aligning a mask with the actual patterns without an automated alignment prior to exposing a photoresist film so that the fabrication process is complex and consumes a long period of time.
A second method is proposed by, for example, JP-A-92-288,868 in which the leakage current from the base region is reduced. In this method, a polysilicon gate electrode of a MOSFET is formed after introducing a dopant into the base region. Subsequently, a second polysilicon layer is sputter-deposited to form an emitter electrode. Only the emitter region is then covered by a photoresist pattern. The second polysilicon layer are then selectively removed by an anisotropic etching so that the emitter electrode and sidewall spacers of the gate electrode are simultaneously formed. In this case, the surface of the base regions is not affected by an anisotropic etching because the base region is located under the second polysilicon layer of the emitter electrode. The second conventional method, however, has a drawback in which a gate length designed for defining a finer pattern to obtain a short channel is substantially increased by the presence of the sidewall spacers, namely the presence of so called auxiliary gate electrodes, since the sidewall spacers formed together with the emitter electrode in a common step are comprised of a conductive polysilicon film. Another drawback is that it is difficult to control the etch rates since an etching of the spacers and the emitter electrode induces also an etching of a gate electrode itself.